There are two types of variable declaration.

1. recursively expanded variables - foo is assigned with bar which inturns assigned to ugh whose value is Huh?

foo = $(bar)
bar = $(ugh)
ugh = Huh?

all:;echo $(foo)

$ make
$ Huh?

2. simply expanded variables - foo is assigned with bar however bar is not defined yet. so it outputs to nothing.

foo := $(bar)
bar := $(ugh)
ugh := Huh?

all:;echo $(foo)

$ make
$

NOTE: To echo something it needs to be in a target. Here the target name is all.

This is a crosspost from my TIL

What the heck is .PHONY in makefile? I have seen this for so long but I always shrugged off. Whatever that is. Well, finally I decided to learn about it.

A bit of introduction to Makefile syntax.

target: prerequisites
<TAB> recipe

The first target in a Makefile will be executed by default when we call make.

blah: blah.o
    cc blah.o -o blah # Runs third

blah.o: blah.c
    cc -c blah.c -o blah.o # Runs second

blah.c:
    echo "int main() { return 0; }" > blah.c # Runs first

In the above example, blah, blah.o and blah.c are targets and they are all files.